A custom ASIC per workflow, not a general accelerator.

We take a customer’s simulation workflow, quantize or distill a state model for it using our own process, and let that process drive the design of the silicon. We ship the hardware with an open source software layer.

Simulation-heavy work runs today on general-purpose GPUs or on unified-memory edge systems. Those systems are fast on average and inconsistent step to step. For simulation, the inconsistency is the real cost: a pipeline that jitters is hard to trust, hard to schedule around, and hard to compare across runs.

So a lot of teams still pay for physical tests in uncontrolled, non-digital environments, because the digital version is not fast or reliable enough to replace them. That is the spend we are going after.

State-space models hold history in a fixed-size state and update it with a fixed amount of work per step. Nothing grows with sequence length. That is a modeling property, and it is also a hardware property: fixed memory, predictable per-step compute, a datapath that can be laid out once and run the same way every time.

Transformers on GPUs do not have this. Their memory footprint grows with context and their latency moves with it. For a solver stepping through time or space, that is the wrong shape.

State models are the right model class for consistent simulation compute, and a state model is regular enough that a small team can build an ASIC around it. We think those two facts belong together.